The present invention relates to a logic circuit which can easily effect a logical function test.
The test of a logic integrated circuit is generally classified into a dc characteristic test for testing a dc characteristic of the circuit, an ac characteristic test for testing an ac characteristic thereof, and a logical function test for testing a logical function thereof. Particularly, the logical function test is necessarily carried out not only in a quality decision test in a mass production line, but also in an acceptance test for a user. It is important to know how to properly and efficiently perform such a logical function test.
Where a test in a mass production line is carried out, there has been adopted in the art a method of bringing a needle into direct contact with a semiconductor chip on which logic integrated circuits are formed to monitor logical states of required nodes. However, with respect to logical integrated circuits which have been increasingly miniaturized, it has been extremely difficult to precisely bring a needle into contact with nodes to be monitored with such a method. Further, there are recently many cases where logic integrated circuits are designed using an automatic placement and routing program. As a result, it has been also difficult to precisely specify a desired node. As stated above, there exist many drawbacks with the method of bringing a needle into direct contact with a semiconductor chip to monitor the status of required nodes.
For facilitating the logical function test, there has been known a method called the LSSD (Level Sensitive Scan Design) technique. According to this method, flip-flops are added to registers in the logic circuit to connect these flip-flops in series, thus to monitor data of respective registers. However, this method can monitor only the data of registers. Namely, only the data indicative of the result output from a combinational circuit can be monitored. Accordingly, where the data indicative of the result is not correct, there is difficulty in specifying which portion in the combinational circuit has failured on the basis of the data indicative of the result. Particularly, in the case of large scale combinational circuits, such a difficulty is serious.
For another system for facilitating the logical function test, the scan pass system and the parallel scan pass system have been known in the art. According to the scan pass system, flip-flops are connected to memory elements e.g. flip-flops or registers etc. connected to a combinational circuit in a logic circuit, respectively, and these flip-flops are connected so as to constitute a shift register. At the time of the logic function test, first one inputs initial data into these memory elements in a test mode to perform a required operation with the combinational circuit in an operational mode; thereafter one reads data indicative of the result from these memory elements in the test mode for a second time. This scan pass system is an extremely effective method in the case where flip-flops are distributed in the logic circuit. However, this system requires the provision of a flip-flop per each flip-flop in the logic circuit, with the result that the additional circuit becomes large when a logic circuit having a large number of flip-flops is used.
On the other hand, the parallel scan system is a system adapted to assign addresses to memory elements e.g. flip-flops or registers etc. to provide an access to these memory elements by making use of the addresses. However, with this system, there is a need to assign addresses to the memory elements from the external or to set addresses to an address register. In addition, for providing an access to the respective memory elements, a circuit for decoding addresses and wiring for delivering an access enable signal to the respective memory elements are required. For this reason, where logic circuits of the parallel scan system are integrated, external terminals for delivering addresses to the memory elements are required and an additional internal wiring is increased.